A conventional type of multi-chip module includes a processor chip and four memory chips mounted side-by-side on an interposer (so-called “2.5D”) that is, in-turn, mounted on a ball grid array (BGA) package substrate. The memory chips are arranged around the periphery of the processor chip. The processor chip and the memory chips are mounted on the interposer and interconnected thereto by respective pluralities of solder joints. The interposer and the package substrate are provided with plural electrical pathways to provide input/output pathways for the semiconductor chips both for inter-chip power, ground and signal propagation as well as input/output from the interposer itself. The semiconductor chips include respective underfill material layers to lessen the effects of differential thermal expansion due to differences in the coefficients of thermal expansion of the chips, the interposer and the solder joints. The interposer is manufactured with multitudes of through-silicon vias (TSVs) to provide pathways between the mounted chips and a package substrate upon which the interposer is mounted. The TSVs and traces are fabricated using large numbers of processing steps.
Although conventional BGA sockets come in many shapes and sizes, there are typically various industry standard sizes and pin outs. Once settled upon, these standard sizes are used over time, sometimes in multitudes of different devices, such as computers, handheld devices and other electronic devices. One example of a conventional BGA socket is an Nvidia SMX2.
Another conventional multi-chip module technology is 2D wafer-level fan-out (or 2D WLFO). Conventional 2D WLFO technology is based on embedding die into a molded wafer, also called “wafer reconstitution.” The molded wafer is processed through a standard wafer level processing flow to create the final integrated circuit assembly structure. The active surface of the dies are coplanar with the mold compound, allowing for the “fan-out” of conductive copper traces and solder ball pads into the molded area using conventional redistribution layer (RDL) processing. Conventional 3D WLFO extends the 2D technology into multi-chip stacking where a second package substrate is mounted on the 2D WLFO.